Y-Junction based addressing in Optical Symmetric Multiprocessor Networks

1. Introduction In a symmetric multiprocessor (SMP), every processor has its own cache, and all the processors and memory modules are connected to the central interconnect, which is usually a shared bus. As the processors become faster, the central interconnect architecture of traditional SMP's impedes performance because it cannot keep up with the processors capabilities. As SMP's have hardware-enforced cache coherence, the snoop bandwidth required for address translation becomes the bottleneck. The growing performance gap between the processor speed and the conventional metal interconnection technology provides the impetus to look at optical technology for solutions. The emerging feasibility of optical interconnects is very promising for signal transmission in digital systems with high data rates at the board level and backplane. This paper proposes an architecture, which is based on scalable binary tree consisting of splitter/combiners for address translation of optical SMP. 1x4 splitters at board level and 1x8 splitters at backplane were designed and simulated using the BPM simulator Prometheus developed by Kymata Software [I]. Optical bus based multiprocessors where processors can simultaneously insert address requests was reported in [2], but in this architecture there is no provision for sharing of data among the processors as the requests are not broadcast. Star coupler has been used in [3], for broadcasting the addresses for writes using snoopy protocols and point-to-point communication for reads. This leads to additional overhead of maintaining the directory for every cache block and moreover, star coupler is used which is not easily scalable. Hence we propose a scalable binary tree consisting of dual Y-junction splitterlcombiner for on-board and backplane interconnection. Optic fibers are used to connect the individual boards to the backplane as shown in figure 1. The splitterhombiner is a dual Y-junction, with the upstream Y-coupler used to combine requests from the processors to the amplifier and the downstream Y-splitter to broadcast the address request to all the modules. This enables broadcasting of memory accesses and hence the requests are serialized when seen by the processors and the memory modules. Optical time division multiplexing is used to serialize the requests, where every processor sends a request during one clock cycle. The addresses are snooped by the processors and the memory modules and appropriate action is taken. Using semiconductor optical amplifier at the root of the tree, which boosts the signal offsets the loss associated with the splitters/couplers. Vertical cavity semiconductor amplifiers at 1. 3 ~ provide …